? semiconductor components industries, llc, 2013 november, 2013 ? rev. 3 1 publication order number: ntmfs4c05n/d ntmfs4c05n power mosfet 30 v, 78 a, single n ? channel, so ? 8 fl features ? low r ds(on) to minimize conduction losses ? low capacitance to minimize driver losses ? optimized gate charge to minimize switching losses ? these devices are pb ? free, halogen free/bfr free and are rohs compliant applications ? cpu power delivery ? dc ? dc converters maximum ratings (t j = 25 c unless otherwise stated) parameter symbol value unit drain ? to ? source voltage v dss 30 v gate ? to ? source voltage v gs 20 v continuous drain current r ja (note 1) steady state t a = 25 c i d 21.7 a t a = 80 c 16.3 power dissipation r ja (note 1) t a = 25 c p d 2.57 w continuous drain current r ja 10 s (note 1) t a = 25 c i d 34.8 a t a = 80 c 26.0 power dissipation r ja 10 s (note 1) t a = 25 c p d 6.6 w continuous drain current r ja (note 2) t a = 25 c i d 11.9 a t a = 80 c 8.9 power dissipation r ja (note 2) t a = 25 c p d 0.77 w continuous drain current r jc (note 1) t c = 25 c i d 78 a t c =80 c 58 power dissipation r jc (note 1) t c = 25 c p d 33 w pulsed drain current t a = 25 c, t p = 10 s i dm 174 a current limited by package t a = 25 c i dmax 80 a operating junction and storage temperature t j , t stg ? 55 to +150 c source current (body diode) i s 30 a drain to source dv/dt dv/d t 7.0 v/ns single pulse drain ? to ? source avalanche energy (t j = 25 c, v gs = 10 v, i l = 41 a pk , l = 0.1 mh, r gs = 25 ) (note 3) e as 84 mj lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. surface ? mounted on fr4 board using 1 sq ? in pad, 1 oz cu. 2. surface ? mounted on fr4 board using the minimum recommended pad size. 3. this is the absolute maximum ratings. parts are 100% tested at t j = 25 c, v gs = 10 v, i l = 29 a, e as = 42 mj. so ? 8 flat lead case 488aa style 1 marking diagram http://onsemi.com a = assembly location y = year w = work week zz = lot traceabililty 4c05n aywzz 1 v (br)dss r ds(on) max i d max 30 v 3.4 m @ 10 v 78 a 5.0 m @ 4.5 v n ? channel mosfet device package shipping ? ordering information NTMFS4C05NT1G so ? 8 fl (pb ? free) 1500 / tape & reel ntmfs4c05nt3g so ? 8 fl (pb ? free) 5000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. s s s g d d d d g (4) s (1,2,3) d (5 ? 8)
ntmfs4c05n http://onsemi.com 2 thermal resistance maximum ratings parameter symbol value unit junction ? to ? case (drain) r jc 3.8 c/w junction ? to ? ambient ? steady state (note 4) r ja 48.6 junction ? to ? ambient ? steady state (note 5) r ja 161.7 junction ? to ? ambient ? (t 10 s) (note 4) r ja 19 4. surface ? mounted on fr4 board using 1 sq ? in pad, 1 oz cu. 5. surface ? mounted on fr4 board using the minimum recommended pad size. electrical characteristics (t j = 25 c unless otherwise specified) parameter symbol test condition min typ max unit off characteristics drain ? to ? source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a 30 v drain ? to ? source breakdown voltage (transient) v (br)dsst v gs = 0 v, i d(aval) = 12.6 a, t case = 25 c, t transient = 100 ns 34 v drain ? to ? source breakdown voltage temperature coefficient v (br)dss / t j 12 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = 24 v t j = 25 c 1.0 a t j = 125 c 10 gate ? to ? source leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 6) gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 1.3 2.2 v negative threshold temperature coefficient v gs(th) /t j 5.1 mv/ c drain ? to ? source on resistance r ds(on) v gs = 10 v i d = 30 a 2.7 3.4 m v gs = 4.5 v i d = 30 a 4.0 5.0 forward transconductance g fs v ds = 1.5 v, i d = 15 a 68 s gate resistance r g t a = 25 c 0.3 1.0 2.0 charges and capacitances input capacitance c iss v gs = 0 v, f = 1 mhz, v ds = 15 v 1972 pf output capacitance c oss 1215 reverse transfer capacitance c rss 59 capacitance ratio c rss /c iss v gs = 0 v, v ds = 15 v, f = 1 mhz 0.030 total gate charge q g(tot) v gs = 4.5 v, v ds = 15 v; i d = 30 a 14 nc threshold gate charge q g(th) 3.3 gate ? to ? source charge q gs 6.0 gate ? to ? drain charge q gd 5.0 gate plateau voltage v gp 3.1 v total gate charge q g(tot) v gs = 10 v, v ds = 15 v; i d = 30 a 30 nc switching characteristics (note 7) turn ? on delay time t d(on) v gs = 4.5 v, v ds = 15 v, i d = 15 a, r g = 3.0 11 ns rise time t r 32 turn ? off delay time t d(off) 21 fall time t f 7.0
ntmfs4c05n http://onsemi.com 3 electrical characteristics (t j = 25 c unless otherwise specified) parameter unit max typ min test condition symbol switching characteristics (note 7) turn ? on delay time t d(on) v gs = 10 v, v ds = 15 v, i d = 15 a, r g = 3.0 8.0 ns rise time t r 26 turn ? off delay time t d(off) 26 fall time t f 5.0 drain ? source diode characteristics forward diode voltage v sd v gs = 0 v, i s = 10 a t j = 25 c 0.77 1.1 v t j = 125 c 0.62 reverse recovery time t rr v gs = 0 v, di s /dt = 100 a/ s, i s = 30 a 40.2 ns charge time t a 20.3 discharge time t b 19.9 reverse recovery charge q rr 30.2 nc product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 6. pulse test: pulse width 300 s, duty cycle 2%. 7. switching characteristics are independent of operating junction temperatures.
ntmfs4c05n http://onsemi.com 4 typical characteristics 10 v figure 1. on ? region characteristics figure 2. transfer characteristics v ds , drain ? to ? source voltage (v) v gs , gate ? to ? source voltage (v) 5 3 2 1 0 0 20 40 60 30 70 4.0 3.5 3.0 2.0 1.5 1.0 figure 3. on ? resistance vs. v gs figure 4. on ? resistance vs. drain current and gate voltage v gs , gate ? to ? source voltage (v) i d , drain current (a) 9.0 8.0 7.0 10 6.0 5.0 4.0 3.0 0.002 0.006 0.010 70 50 30 60 40 20 0.004 0.005 0.007 0.008 0.002 figure 5. on ? resistance variation with temperature figure 6. drain ? to ? source leakage current vs. voltage t j , junction temperature ( c) v ds , drain ? to ? source voltage (v) 150 125 100 75 25 0 ? 25 ? 50 0.8 1.0 1.1 1.3 30 25 20 15 10 5 10 100 1000 10000 i d , drain current (a) i d , drain current (a) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , drain ? to ? source res- istance (normalized) i dss , leakage (na) 90 10 4 v to 6.5 v 3.6 v 3.2 v 3.0 v 2.8 v 2.6 v 3.8 v t j = 25 c v ds = 5 v t j = 25 c t j = 125 c t j = ? 55 c 0.008 0.006 i d = 30 a t j = 25 c v gs = 4.5 v t j = 25 c v gs = 10 v 50 i d = 30 a v gs = 10 v v gs = 0 v t j = 85 c t j = 150 c t j = 125 c 2.5 0.004 0.014 0.012 1.2 1.4 0.7 1.5 50 0.016 80 10 3.4 v 110 120 140 100 130 4 0 20 40 60 30 70 90 10 50 80 110 120 140 100 130 4.5 0.5 0 0.020 0.024 0.022 0.018 0.028 0.026 0.003 1.6 1.7 0.9
ntmfs4c05n http://onsemi.com 5 typical characteristics figure 7. capacitance variation figure 8. gate ? to ? source and drain ? to ? source voltage vs. total charge v ds , drain ? to ? source voltage (v) q g , total gate charge (nc) 25 20 15 10 30 5 0 0 250 1000 1250 figure 9. resistive switching time variation vs. gate resistance figure 10. diode forward voltage vs. current r g , gate resistance ( ) v sd , source ? to ? drain voltage (v) 100 10 1 1 10 100 1000 0.9 0.8 0.7 0.6 0.5 0.4 0 2 4 6 8 10 12 figure 11. maximum rated forward biased safe operating area figure 12. maximum avalanche energy vs. starting junction temperature v ds , drain ? to ? source voltage (v) t j , starting junction temperature ( c) 100 10 1 0.1 0.01 1 10 100 1000 150 125 100 75 50 25 0 5 20 30 c, capacitance (pf) v gs , gate ? to ? source voltage (v) t, time (ns) i s , source current (a) i d , drain current (a) e as , single pulse drain ? to ? source avalanche energy (mj) v gs = 0 v t j = 25 c c iss c oss c rss q t q gs q gd v dd = 15 v i d = 15 a v gs = 10 v t d(off) t d(on) t r t f t j = 25 c t j = 125 c v gs = 0 v 0 v < v gs < 10 v single pulse t c = 25 c r ds(on) limit thermal limit package limit 100 s 10 ms 1 ms dc i d = 29 a 1750 2500 10 15 25 45 500 750 1500 2000 2250 35 40 3000 2750 1.0 0 2 4 6 8 10 0 4 8 121620242832 t j = 25 c v dd = 15 v v gs = 10 v i d = 30 a 14 16 18 20 10 s 0.01 0.1
ntmfs4c05n http://onsemi.com 6 typical characteristics figure 13. thermal response pulse time (sec) 0.01 0.001 0.0001 0.00001 0.000001 0.01 0.1 1 10 100 r(t) ( c/w) 0.1 1 10 100 1000 10% duty cycle = 50% 20% 5% 2% 1% single pulse figure 14. g fs vs. i d i d (a) 40 30 10 0 0 20 100 g fs (s) 20 50 40 60 80 60 80 120 70 figure 15. avalanche characteristics pulse width (seconds) 1.e ? 03 1.e ? 04 1.e ? 06 1.e ? 07 1 10 100 i d , drain current (a) 1.e ? 05 t a = 25 c t a = 85 c
ntmfs4c05n http://onsemi.com 7 package dimensions m 3.00 3.40 0 ??? 3.80 12 dfn5 5x6, 1.27p (so ? 8fl) case 488aa issue h notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeter. 3. dimension d1 and e1 do not include mold flash protrusions or gate burrs. 1234 top view side view bottom view d1 e1 d e 2 2 b a 0.20 c 0.20 c 2 x 2 x dim min nom millimeters a 0.90 1.00 a1 0.00 ??? b 0.33 0.41 c 0.23 0.28 d 5.15 bsc d1 4.70 4.90 d2 3.80 4.00 e 6.15 bsc e1 5.70 5.90 e2 3.45 3.65 e 1.27 bsc g 0.51 0.61 k 1.20 1.35 l 0.51 0.61 l1 0.05 0.17 a 0.10 c 0.10 c detail a 14 l1 e/2 8x d2 g e2 k b a 0.10 b c 0.05 c l detail a a1 e 3 x c 4 x c seating plane max 1.10 0.05 0.51 0.33 5.10 4.20 6.10 3.85 0.71 1.50 0.71 0.20 style 1: pin 1. source 2. source 3. source 4. gate 5. drain m *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 1.270 2x 0.750 1.000 0.905 0.475 4.530 1.530 4.560 0.495 3.200 1.330 0.965 2x 2x 3x 4x 4x pin 5 (exposed pad) on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ntmfs4c05n/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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